loading...
 This Article 
   
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
The 2002 IEEE International Workshop on Memory Technology, Design and Testing (MTDT 2002)
Decreasing EEPROM Programming Bias With Negative Voltage, Reliability Impact
Isle of Bendor, France
July 10-July 12
ISBN: 0-7695-1617-3
ASCII Text
x 
 
R. Laffont, J. Razafindramora, P. Canet, R. Bouchakour, J. M. Mirabel, "Decreasing EEPROM Programming Bias With Negative Voltage, Reliability Impact," Memory Technology, Design and Testin, IEEE International Workshop on, pp. 168, The 2002 IEEE International Workshop on Memory Technology, Design and Testing (MTDT 2002), 2002.
 
 
BibTex
x
 
@article{ 10.1109/MTDT.2002.1029781,
author = {R. Laffont and J. Razafindramora and P. Canet and R. Bouchakour and J. M. Mirabel},
title = {Decreasing EEPROM Programming Bias With Negative Voltage, Reliability Impact},
journal ={Memory Technology, Design and Testin, IEEE International Workshop on},
volume = {0},
year = {2002},
issn = {1087-4852},
pages = {168},
doi = {http://doi.ieeecomputersociety.org/10.1109/MTDT.2002.1029781},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Memory Technology, Design and Testin, IEEE International Workshop on
TI - Decreasing EEPROM Programming Bias With Negative Voltage, Reliability Impact
SN - 1087-4852
SP
EP
A1 - R. Laffont,
A1 - J. Razafindramora,
A1 - P. Canet,
A1 - R. Bouchakour,
A1 - J. M. Mirabel,
PY - 2002
KW - null
VL - 0
JA - Memory Technology, Design and Testin, IEEE International Workshop on
ER -
 
R. Laffont, L2MP/Polytech-UMR CNRS and ST-Microelectronics
J. Razafindramora, L2MP/Polytech-UMR CNRS
P. Canet, L2MP/Polytech-UMR CNRS
R. Bouchakour, L2MP/Polytech-UMR CNRS
J. M. Mirabel, ST-Microelectronics
This paper presents a study of EEPROM cell programming in order to decrease the bias polarization of the memory cell. Simulations show that it is possible to erase and write a cell with a divide up polarization, with positive and negative pulses. Measurements on a memory cell confirm these statements. Moreover simulations of the electrical field through the tunnel oxide didn?t show any change of the maximum value, that means there is no impact on cells reliability. Endurance tests were performed on several memory cells with divide up polarizations. They show the same results as classical programming
Citation:
R. Laffont, J. Razafindramora, P. Canet, R. Bouchakour, J. M. Mirabel, "Decreasing EEPROM Programming Bias With Negative Voltage, Reliability Impact," mtdt, pp.168, The 2002 IEEE International Workshop on Memory Technology, Design and Testing (MTDT 2002), 2002
Usage of this product signifies your acceptance of the Terms of Use.