Design and Test of a 9-port SRAM for a 100Gb/s STS-1 Switch

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The 2002 IEEE International Workshop on Memory Technology, Design and Testing (MTDT 2002)

Isle of Bendor, France

July 10-July 12

ISBN: 0-7695-1617-3

	ASCII Text	x
	Robert Gibbins, R. Dean Adams, Thomas Eckenrode, Michael Ouellette, Yuejian Wu, "Design and Test of a 9-port SRAM for a 100Gb/s STS-1 Switch," Memory Technology, Design and Testin, IEEE International Workshop on, pp. 83, The 2002 IEEE International Workshop on Memory Technology, Design and Testing (MTDT 2002), 2002.

	BibTex	x
	@article{ 10.1109/MTDT.2002.1029767, author = {Robert Gibbins and R. Dean Adams and Thomas Eckenrode and Michael Ouellette and Yuejian Wu}, title = {Design and Test of a 9-port SRAM for a 100Gb/s STS-1 Switch}, journal ={Memory Technology, Design and Testin, IEEE International Workshop on}, volume = {0}, year = {2002}, issn = {1087-4852}, pages = {83}, doi = {http://doi.ieeecomputersociety.org/10.1109/MTDT.2002.1029767}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Memory Technology, Design and Testin, IEEE International Workshop on TI - Design and Test of a 9-port SRAM for a 100Gb/s STS-1 Switch SN - 1087-4852 SP EP A1 - Robert Gibbins, A1 - R. Dean Adams, A1 - Thomas Eckenrode, A1 - Michael Ouellette, A1 - Yuejian Wu, PY - 2002 KW - null VL - 0 JA - Memory Technology, Design and Testin, IEEE International Workshop on ER -

Robert Gibbins, Nortel Networks

R. Dean Adams, IBM Microelectronics

Thomas Eckenrode, IBM Microelectronics

Michael Ouellette, IBM Microelectronics

Yuejian Wu, Nortel Networks

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MTDT.2002.1029767

This paper presents the design, fault modeling, and BIST solution of an application specific 9-port SRAM. The use of the 9-port SRAM in place of more conventional memory in a 100Gb/s SONET switch ASIC resulted in calculated reductions of 43% in die size, 31% in power consumption and 75% in data memory bit count. A custom programmable BIST solution was implemented that takes into consideration the memory?s special features such as the large number of ports, large read-to-write port asymmetry and the TDM read scheme.

Citation:

Robert Gibbins, R. Dean Adams, Thomas Eckenrode, Michael Ouellette, Yuejian Wu, "Design and Test of a 9-port SRAM for a 100Gb/s STS-1 Switch," mtdt, pp.83, The 2002 IEEE International Workshop on Memory Technology, Design and Testing (MTDT 2002), 2002

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