A high speed 15 ns 4 Mbits asynchronous SRAM, 500 ?A stand-by current, 300 Krads total dose tolerant, has been developed for space applications, using a hardened 0.25 micron 4 layers metal full CMOS process. A hierarchical organisation per IO bits has been used to achieve high speed as well as low dynamic consumption, also suited for simple SEU (single event upset) induced error corrections, allowing mitigation with classical EDAC corrector. The product operates within 3 to 3.6V, and ambient temperature from -55 to +125?C. A high density die size of 68,3 mm 2 allows the use of a specific 36-pins dual in line flat pack package with a 500 mils width, making this product very competitive against SEU hardened chips. Sucessful silicon results are presented as well as radiation tests up to 300 Krads.