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The 2002 IEEE International Workshop on Memory Technology, Design and Testing (MTDT 2002)
A Scan-Bist Environment for Testing Embedded Memories
Isle of Bendor, France
July 10-July 12
ISBN: 0-7695-1617-3
ASCII Text
x 
 
F. Karimi, F. Lombardi, "A Scan-Bist Environment for Testing Embedded Memories," Memory Technology, Design and Testin, IEEE International Workshop on, pp. 17, The 2002 IEEE International Workshop on Memory Technology, Design and Testing (MTDT 2002), 2002.
 
 
BibTex
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@article{ 10.1109/MTDT.2002.1029758,
author = {F. Karimi and F. Lombardi},
title = {A Scan-Bist Environment for Testing Embedded Memories},
journal ={Memory Technology, Design and Testin, IEEE International Workshop on},
volume = {0},
year = {2002},
issn = {1087-4852},
pages = {17},
doi = {http://doi.ieeecomputersociety.org/10.1109/MTDT.2002.1029758},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
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TY - CONF
JO - Memory Technology, Design and Testin, IEEE International Workshop on
TI - A Scan-Bist Environment for Testing Embedded Memories
SN - 1087-4852
SP
EP
A1 - F. Karimi,
A1 - F. Lombardi,
PY - 2002
KW - null
VL - 0
JA - Memory Technology, Design and Testin, IEEE International Workshop on
ER -
 
F. Karimi, LTX Corporation
F. Lombardi, Northeastern University
This paper presents a new IEEE 1149.1 compatible architecture as an intermediate environment for testing embedded memories. A BIST structure and a boundary scan are used for testing various memory configurations for programmability as well as improved controllability and observability. Its novelty is that features such as modularity, scalability with word size and adaptability to different memory configurations and testing requirements, are accomplished at relative ease. In the boundary scan, user-defined test modes are utilized so that basic modications to the elements of a seed algorithm can be generated very efficiently.
Citation:
F. Karimi, F. Lombardi, "A Scan-Bist Environment for Testing Embedded Memories," mtdt, pp.17, The 2002 IEEE International Workshop on Memory Technology, Design and Testing (MTDT 2002), 2002
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