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The 2002 IEEE International Workshop on Memory Technology, Design and Testing (MTDT 2002)
Defect-Oriented Analysis of Memory BIST Tests
Isle of Bendor, France
July 10-July 12
ISBN: 0-7695-1617-3
ASCII Text
x 
 
Alvin Jee, "Defect-Oriented Analysis of Memory BIST Tests," Memory Technology, Design and Testin, IEEE International Workshop on, pp. 7, The 2002 IEEE International Workshop on Memory Technology, Design and Testing (MTDT 2002), 2002.
 
 
BibTex
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@article{ 10.1109/MTDT.2002.1029756,
author = {Alvin Jee},
title = {Defect-Oriented Analysis of Memory BIST Tests},
journal ={Memory Technology, Design and Testin, IEEE International Workshop on},
volume = {0},
year = {2002},
issn = {1087-4852},
pages = {7},
doi = {http://doi.ieeecomputersociety.org/10.1109/MTDT.2002.1029756},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Memory Technology, Design and Testin, IEEE International Workshop on
TI - Defect-Oriented Analysis of Memory BIST Tests
SN - 1087-4852
SP
EP
A1 - Alvin Jee,
PY - 2002
KW - null
VL - 0
JA - Memory Technology, Design and Testin, IEEE International Workshop on
ER -
 
Alvin Jee, HPL, Inc.
This paper describes a defect-oriented analysis of 4 BIST tests that are used to test a commercial 6-port embedded SRAM. We will examine the realistic fault and defect coverages of these memory BIST tests. We also uncover the subtle effect that addressing order has on the coverage that a test can provide. In addition, we will show that the coverage that a test provides can vary from row to row depending on the addressing scheme.
Citation:
Alvin Jee, "Defect-Oriented Analysis of Memory BIST Tests," mtdt, pp.7, The 2002 IEEE International Workshop on Memory Technology, Design and Testing (MTDT 2002), 2002
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