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International Workshop on Memory Technology, Design, and Testing (MTDT'01)
Realistic Fault Models and Test Procedures for Multi-Port SRAMs
San Jose, California
August 06-August 07
ISBN: 0-7695-1242-9
ASCII Text
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Said Hamdioui, Ad J. van de Goor, David Eastwick, Mike Rodgers, "Realistic Fault Models and Test Procedures for Multi-Port SRAMs," Memory Technology, Design and Testin, IEEE International Workshop on, pp. 0065, International Workshop on Memory Technology, Design, and Testing (MTDT'01), 2001.
 
 
BibTex
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@article{ 10.1109/MTDT.2001.945230,
author = {Said Hamdioui and Ad J. van de Goor and David Eastwick and Mike Rodgers},
title = {Realistic Fault Models and Test Procedures for Multi-Port SRAMs},
journal ={Memory Technology, Design and Testin, IEEE International Workshop on},
volume = {0},
year = {2001},
isbn = {0-7695-1242-9},
pages = {0065},
doi = {http://doi.ieeecomputersociety.org/10.1109/MTDT.2001.945230},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Memory Technology, Design and Testin, IEEE International Workshop on
TI - Realistic Fault Models and Test Procedures for Multi-Port SRAMs
SN - 0-7695-1242-9
SP
EP
A1 - Said Hamdioui,
A1 - Ad J. van de Goor,
A1 - David Eastwick,
A1 - Mike Rodgers,
PY - 2001
VL - 0
JA - Memory Technology, Design and Testin, IEEE International Workshop on
ER -
 
Said Hamdioui, Intel Corporation
Ad J. van de Goor, Delft University of Technology
David Eastwick, Intel Corporation
Mike Rodgers, Intel Corporation
Abstract: This paper presents realistic fault models for multi-port memories with p ports, based on defect injection and SPICE simulation. The results show that the fault models for p-port memories consist of p classes: single-port faults, two-port faults,..., p-port faults. In addition, the paper discusses the test procedure for such memories. It shows that the time complexity of the required tests is not exponentially proportional with p, as published by different authors, but it is linear; irrespective of the number of ports the multi-port memory consists of.
Citation:
Said Hamdioui, Ad J. van de Goor, David Eastwick, Mike Rodgers, "Realistic Fault Models and Test Procedures for Multi-Port SRAMs," mtdt, pp.0065, International Workshop on Memory Technology, Design, and Testing (MTDT'01), 2001
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