An Approach for Evaluation of Redunancy Analysis Algorithms

M
MTDT
2001
International Workshop on Memory Technology, Design, and Testing (MTDT'01)
Abstract - An Approach for Evaluation of Redunancy Analysis Algorithms

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International Workshop on Memory Technology, Design, and Testing (MTDT'01)

San Jose, California

August 06-August 07

ISBN: 0-7695-1242-9

	ASCII Text	x
	S. Shoukourian, V. Vardanian, Y. Zorian, "An Approach for Evaluation of Redunancy Analysis Algorithms," Memory Technology, Design and Testin, IEEE International Workshop on, pp. 0051, International Workshop on Memory Technology, Design, and Testing (MTDT'01), 2001.

	BibTex	x
	@article{ 10.1109/MTDT.2001.945228, author = {S. Shoukourian and V. Vardanian and Y. Zorian}, title = {An Approach for Evaluation of Redunancy Analysis Algorithms}, journal ={Memory Technology, Design and Testin, IEEE International Workshop on}, volume = {0}, year = {2001}, isbn = {0-7695-1242-9}, pages = {0051}, doi = {http://doi.ieeecomputersociety.org/10.1109/MTDT.2001.945228}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Memory Technology, Design and Testin, IEEE International Workshop on TI - An Approach for Evaluation of Redunancy Analysis Algorithms SN - 0-7695-1242-9 SP EP A1 - S. Shoukourian, A1 - V. Vardanian, A1 - Y. Zorian, PY - 2001 VL - 0 JA - Memory Technology, Design and Testin, IEEE International Workshop on ER -

S. Shoukourian, Virage Logic Int.

V. Vardanian, Virage Logic Int.

Y. Zorian, Virage Logic Corp.

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MTDT.2001.945228

Abstract: An approach for design and evaluation of redundancy analysis algorithms based on vectors of preferences is proposed for memory devices with spare elements. Experiments on the application of the new algorithms for Self-Test and Repair (STAR) type SRAM memories have shown the efficiency of the proposed approach.

Citation:

S. Shoukourian, V. Vardanian, Y. Zorian, "An Approach for Evaluation of Redunancy Analysis Algorithms," mtdt, pp.0051, International Workshop on Memory Technology, Design, and Testing (MTDT'01), 2001

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