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International Workshop on Memory Technology, Design, and Testing (MTDT'01)
A Method to Caculate Redundancy Coverage for FLASH Memory
San Jose, California
August 06-August 07
ISBN: 0-7695-1242-9
ASCII Text
x 
 
S. Matarrese, L. Fasoli, "A Method to Caculate Redundancy Coverage for FLASH Memory," Memory Technology, Design and Testin, IEEE International Workshop on, pp. 0041, International Workshop on Memory Technology, Design, and Testing (MTDT'01), 2001.
 
 
BibTex
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@article{ 10.1109/MTDT.2001.945226,
author = {S. Matarrese and L. Fasoli},
title = {A Method to Caculate Redundancy Coverage for FLASH Memory},
journal ={Memory Technology, Design and Testin, IEEE International Workshop on},
volume = {0},
year = {2001},
isbn = {0-7695-1242-9},
pages = {0041},
doi = {http://doi.ieeecomputersociety.org/10.1109/MTDT.2001.945226},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Memory Technology, Design and Testin, IEEE International Workshop on
TI - A Method to Caculate Redundancy Coverage for FLASH Memory
SN - 0-7695-1242-9
SP
EP
A1 - S. Matarrese,
A1 - L. Fasoli,
PY - 2001
VL - 0
JA - Memory Technology, Design and Testin, IEEE International Workshop on
ER -
 
S. Matarrese, STMicroelectronics
L. Fasoli, STMicroelectronics
Abstract: This paper presents a method to calculate the redundancy coverage for FLASH memory. The method can be used to compare different redundancy architectures and gives the probability to be able to repair a certain number of random fails. After a brief introduction, the hypothesis and the method will be presented. Few illustrative examples are provided.
Citation:
S. Matarrese, L. Fasoli, "A Method to Caculate Redundancy Coverage for FLASH Memory," mtdt, pp.0041, International Workshop on Memory Technology, Design, and Testing (MTDT'01), 2001
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