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International Workshop on Memory Technology, Design, and Testing (MTDT'01)
Orthogonal Transpose-RAM Cell Array Architecture with Alternate Bit-Line To Bit-Line Contact Scheme
San Jose, California
August 06-August 07
ISBN: 0-7695-1242-9
ASCII Text
x 
 
Kyung-Saeng Kim, KwangMyoung Rho, Kwyro Lee, "Orthogonal Transpose-RAM Cell Array Architecture with Alternate Bit-Line To Bit-Line Contact Scheme," Memory Technology, Design and Testin, IEEE International Workshop on, pp. 0009, International Workshop on Memory Technology, Design, and Testing (MTDT'01), 2001.
 
 
BibTex
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@article{ 10.1109/MTDT.2001.945222,
author = {Kyung-Saeng Kim and KwangMyoung Rho and Kwyro Lee},
title = {Orthogonal Transpose-RAM Cell Array Architecture with Alternate Bit-Line To Bit-Line Contact Scheme},
journal ={Memory Technology, Design and Testin, IEEE International Workshop on},
volume = {0},
year = {2001},
isbn = {0-7695-1242-9},
pages = {0009},
doi = {http://doi.ieeecomputersociety.org/10.1109/MTDT.2001.945222},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Memory Technology, Design and Testin, IEEE International Workshop on
TI - Orthogonal Transpose-RAM Cell Array Architecture with Alternate Bit-Line To Bit-Line Contact Scheme
SN - 0-7695-1242-9
SP
EP
A1 - Kyung-Saeng Kim,
A1 - KwangMyoung Rho,
A1 - Kwyro Lee,
PY - 2001
VL - 0
JA - Memory Technology, Design and Testin, IEEE International Workshop on
ER -
 
Kyung-Saeng Kim, Korea Advanced Institute of Science and Technology (KAIST)
KwangMyoung Rho, Korea Advanced Institute of Science and Technology (KAIST)
Kwyro Lee, Korea Advanced Institute of Science and Technology (KAIST)
Abstract: An orthogonal RAM cell array architecture suitable for efficient transposing is proposed, and layout and simulation results are presented. The cell is developed to adopt folded bit-line sensing scheme area-efficiently. The proposed alternate bit-line to bit-line contact scheme in the orthogonal RAM cell array architecture leads to asymmetric bit-line sensing scheme and (i, 2i) bit-line transposing scheme, and results in fast response time of the sense amplifier and low power dissipation for restoring.
Citation:
Kyung-Saeng Kim, KwangMyoung Rho, Kwyro Lee, "Orthogonal Transpose-RAM Cell Array Architecture with Alternate Bit-Line To Bit-Line Contact Scheme," mtdt, pp.0009, International Workshop on Memory Technology, Design, and Testing (MTDT'01), 2001
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