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2000 IEEE International Workshop on Memory Technology, Design and Testing (MTDT'00)
Defect Analysis and Realistic Fault Model Extensions for Static Random Access Memories
San Jose, California
August 07-August 08
ISBN: 0-7695-0689-5
ASCII Text
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Kamran Zarrineh, R. Dean Adams, Aneesha P . Deo, "Defect Analysis and Realistic Fault Model Extensions for Static Random Access Memories," Memory Technology, Design and Testin, IEEE International Workshop on, pp. 119, 2000 IEEE International Workshop on Memory Technology, Design and Testing (MTDT'00), 2000.
 
 
BibTex
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@article{ 10.1109/MTDT.2000.868625,
author = {Kamran Zarrineh and R. Dean Adams and Aneesha P . Deo},
title = {Defect Analysis and Realistic Fault Model Extensions for Static Random Access Memories},
journal ={Memory Technology, Design and Testin, IEEE International Workshop on},
volume = {0},
year = {2000},
issn = {1087-4852},
pages = {119},
doi = {http://doi.ieeecomputersociety.org/10.1109/MTDT.2000.868625},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Memory Technology, Design and Testin, IEEE International Workshop on
TI - Defect Analysis and Realistic Fault Model Extensions for Static Random Access Memories
SN - 1087-4852
SP
EP
A1 - Kamran Zarrineh,
A1 - R. Dean Adams,
A1 - Aneesha P . Deo,
PY - 2000
VL - 0
JA - Memory Technology, Design and Testin, IEEE International Workshop on
ER -
 
Kamran Zarrineh, IBM Microelectronics
R. Dean Adams, IBM Microelectronics
Aneesha P . Deo, State University of New York at Buffalo
Digital systems are composed of data paths, control paths and memories. The recent advancements in VLSI technology and high memory demand of today's VLSI systems have made embedded memories very common in digital systems.The ways that a memory can fail depends on the behavior of its components. A vertical slice of an SRAM consists of 1) a sense amplifier, 2) an isolation and pre-charge circuit, 3) one or more memory cells and 4) a write head as shown in Figure 1. A memory also has an address decoder, which could be designed with static or dynamic logic.
Citation:
Kamran Zarrineh, R. Dean Adams, Aneesha P . Deo, "Defect Analysis and Realistic Fault Model Extensions for Static Random Access Memories," mtdt, pp.119, 2000 IEEE International Workshop on Memory Technology, Design and Testing (MTDT'00), 2000
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