2000 IEEE International Workshop on Memory Technology, Design and Testing (MTDT'00) A Low Voltage Embedded Single Port SRAM Generator in a 0.18?m Standard CMOS Process San Jose, California August 07-August 08 ISBN: 0-7695-0689-5
A low voltage embedded single port SRAM memory generator implemented in a 6 metals, 0.18um standard CMOS process is described. The typical (8kx16) cut is achieving 300Mhz maximum frequency, with a 3.3ns access time at 1.3V and 25°C and a typical power of 60A/Mhz at 1.3V. Special care has been taken to reduce the standby current as well. The hierarchical wordline architecture and a differential output bus allow low power characteristics. At the same time high speed is reached, especially thanks to a novel dynamic wordline decoder. The generator ranges from 1Kbit to 2Mbit and features an optional programmable redundancy.
Citation:
C. Frey, F. Genevaux, C. Issartel, D. Turgis, Jp. Schoellkopf, "A Low Voltage Embedded Single Port SRAM Generator in a 0.18?m Standard CMOS Process," mtdt, pp.106, 2000 IEEE International Workshop on Memory Technology, Design and Testing (MTDT'00), 2000 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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