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2000 IEEE International Workshop on Memory Technology, Design and Testing (MTDT'00)
Synchronous Dynamic Memory Test Construction: A Field Approach
San Jose, California
August 07-August 08
ISBN: 0-7695-0689-5
ASCII Text
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Joerg Vollrath, "Synchronous Dynamic Memory Test Construction: A Field Approach," Memory Technology, Design and Testin, IEEE International Workshop on, pp. 59, 2000 IEEE International Workshop on Memory Technology, Design and Testing (MTDT'00), 2000.
 
 
BibTex
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@article{ 10.1109/MTDT.2000.868616,
author = {Joerg Vollrath},
title = {Synchronous Dynamic Memory Test Construction: A Field Approach},
journal ={Memory Technology, Design and Testin, IEEE International Workshop on},
volume = {0},
year = {2000},
issn = {1087-4852},
pages = {59},
doi = {http://doi.ieeecomputersociety.org/10.1109/MTDT.2000.868616},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
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TY - CONF
JO - Memory Technology, Design and Testin, IEEE International Workshop on
TI - Synchronous Dynamic Memory Test Construction: A Field Approach
SN - 1087-4852
SP
EP
A1 - Joerg Vollrath,
PY - 2000
VL - 0
JA - Memory Technology, Design and Testin, IEEE International Workshop on
ER -
 
Joerg Vollrath, White Oak Semiconductor
This paper gives an introduction how to construct dynamic memory tests and test flows. Systematically a basic march test is developed choosing a pattern, voltage levels and timings. Starting with this basic pattern, modifications for characterization, diagnostic and speed testing are discussed. These variations are then used to construct a test sequence to ensure functionality according to the data sheet specification.
Citation:
Joerg Vollrath, "Synchronous Dynamic Memory Test Construction: A Field Approach," mtdt, pp.59, 2000 IEEE International Workshop on Memory Technology, Design and Testing (MTDT'00), 2000
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