In flash memories, separate biasing of the source line and, in the case of a triple well process, of the well terminals of each sector, is required to prevent electrical stress of unselected sectors. This paper presents a hierarchical biasing architecture developed for this purpose. The lines carrying the voltages to be applied to the terminals of all the sectors in the same row are routed horizontally nearby the respective row. A vertical line controls the connection of the terminals of all sectors in the same column to the required bias lines. The proposed biasing organization allows silicon area saving thanks to simplified routing and reduced number of high voltage switches. The presented biasing architecture has been successfully used in a 64-Mbit 2-bit/cell NOR-type Flash memory and has been integrated in 0.18?m CMOS fabrication process.