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2000 IEEE International Workshop on Memory Technology, Design and Testing (MTDT'00)
Optimizing Memory Tests by Analyzing Defect Coverage
San Jose, California
August 07-August 08
ISBN: 0-7695-0689-5
ASCII Text
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Alvin Jee, Jonathon E. Colburn, V. Swamy Irrinki, Mukesh Puri, "Optimizing Memory Tests by Analyzing Defect Coverage," Memory Technology, Design and Testin, IEEE International Workshop on, pp. 20, 2000 IEEE International Workshop on Memory Technology, Design and Testing (MTDT'00), 2000.
 
 
BibTex
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@article{ 10.1109/MTDT.2000.868611,
author = {Alvin Jee and Jonathon E. Colburn and V. Swamy Irrinki and Mukesh Puri},
title = {Optimizing Memory Tests by Analyzing Defect Coverage},
journal ={Memory Technology, Design and Testin, IEEE International Workshop on},
volume = {0},
year = {2000},
issn = {1087-4852},
pages = {20},
doi = {http://doi.ieeecomputersociety.org/10.1109/MTDT.2000.868611},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Memory Technology, Design and Testin, IEEE International Workshop on
TI - Optimizing Memory Tests by Analyzing Defect Coverage
SN - 1087-4852
SP
EP
A1 - Alvin Jee,
A1 - Jonathon E. Colburn,
A1 - V. Swamy Irrinki,
A1 - Mukesh Puri,
PY - 2000
VL - 0
JA - Memory Technology, Design and Testin, IEEE International Workshop on
ER -
 
Alvin Jee, HPL, Inc.
V. Swamy Irrinki, LSI Logic
Mukesh Puri, LSI Logic
This paper describes how analyzing the defect coverage of memory tests can lead to optimized test coverage and test application time before the device reaches production. A 9- port embedded SRAM will be used as the example memory for this paper. We will analyze four different functional tests and show that using just two of the four tests provides nearly all the defect coverage of all four tests, but requires a fraction of the test application time. We will also show that a more complete test set should contain non-simultaneous port accesses and time-dependent tests.
Citation:
Alvin Jee, Jonathon E. Colburn, V. Swamy Irrinki, Mukesh Puri, "Optimizing Memory Tests by Analyzing Defect Coverage," mtdt, pp.20, 2000 IEEE International Workshop on Memory Technology, Design and Testing (MTDT'00), 2000
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