1999 IEEE International Workshop on Memory Technology, Design, and Testing Computing in Memory Architectures for Digital Image Processing San Jose, California August 09-August 10 ISBN: 0-7695-0259-8
Continuing improvements in semiconductor fabrication density are enabling new classes of System-on-a-Chip architectures that combine extensive processing logic and high-density memory. Many of the capabilities of these new architectures can be custom tailored to the demands of real-time digital image processing. This paper evaluates several candidate designs, using the criteria of image processing performance, flexibility, manufacturability, and fabrication cost.
Citation:
Luke Roth Lee Coraor, David Landis, Paul Hulina, Scott Deno, "Computing in Memory Architectures for Digital Image Processing," mtdt, pp.8, 1999 IEEE International Workshop on Memory Technology, Design, and Testing, 1999 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||