Teaching Pipelining and Concurrency using Hardware Description Languages

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	Similar Articles Articles by Tsai Chi Huang Articles by Sudhakar Yalamanchili Articles by Roy W. Melton Articles by Philip R. Bingham Articles by Cecil O. Alford

IEEE International Conference on Microelectronic Systems Education

Arlington, Virginia

July 19-July 21

ISBN: 0-7695-0312-8

	ASCII Text	x
	Tsai Chi Huang, Sudhakar Yalamanchili, Roy W. Melton, Philip R. Bingham, Cecil O. Alford, "Teaching Pipelining and Concurrency using Hardware Description Languages," Microelectronics Systems Education, IEEE International Conference on/Multimedia Software Engineering, International Symposium on, pp. 55, IEEE International Conference on Microelectronic Systems Education, 1999.

	BibTex	x
	@article{ 10.1109/MSE.1999.787035, author = {Tsai Chi Huang and Sudhakar Yalamanchili and Roy W. Melton and Philip R. Bingham and Cecil O. Alford}, title = {Teaching Pipelining and Concurrency using Hardware Description Languages}, journal ={Microelectronics Systems Education, IEEE International Conference on/Multimedia Software Engineering, International Symposium on}, volume = {0}, year = {1999}, issn = {1530-2024}, pages = {55}, doi = {http://doi.ieeecomputersociety.org/10.1109/MSE.1999.787035}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Microelectronics Systems Education, IEEE International Conference on/Multimedia Software Engineering, International Symposium on TI - Teaching Pipelining and Concurrency using Hardware Description Languages SN - 1530-2024 SP EP A1 - Tsai Chi Huang, A1 - Sudhakar Yalamanchili, A1 - Roy W. Melton, A1 - Philip R. Bingham, A1 - Cecil O. Alford, PY - 1999 VL - 0 JA - Microelectronics Systems Education, IEEE International Conference on/Multimedia Software Engineering, International Symposium on ER -

Tsai Chi Huang

Sudhakar Yalamanchili

Roy W. Melton

Philip R. Bingham

Cecil O. Alford

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MSE.1999.787035

Relating to a previous simplified VHDL processor model [1], a more advanced synthesized VHDL pipeline microprocessor model was developed and has been used in the second term computer architecture course offered in the School of Electrical and Computer Engineering at the Georgia Institute of Techonology. This paper will first describe the pipeline processor model and its VHDL implementation. Then, it presents various implementation extensions that have been assigned and completed within a satisfactory period by participating students.

Citation:

Tsai Chi Huang, Sudhakar Yalamanchili, Roy W. Melton, Philip R. Bingham, Cecil O. Alford, "Teaching Pipelining and Concurrency using Hardware Description Languages," mse, pp.55, IEEE International Conference on Microelectronic Systems Education, 1999

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