The paper presents a Distributed Interactive Pedagogical Simulator (DIPS) dedicated to EECS. The simulator implements a multimedia/Java/Corba instrumentation of the famous Patterson & Hennessy MIPS multicycle core. For each microprocessor cycle, the key principle is to compare the simulation state vector produced by an integrated VHDL kernel simulator (ie the reference) to the one produced by the collaborative work of the learners over a LAN. Each learner is responsible for one functionnal unit (Datapath, control FSM, memory), and has to mimic manually its behaviour through a graphic user interface. At the end of a cycle, feed-back and error report is sent personnally to each learner.