Parallelization following the replic ate d worker principle can significantly acceler ate functional logic simulation of micropr ocessor structures. Successful applic ationof this method strongly depends on circuit model partitioning. We have developed a hierarchical partitioning strategy with prepartitioning and main partitioning as core phases that appear as bottom-up cone clustering. Cones can b eseen as special areas of combinational logic which have the ability to directly in uence storing or output elements of a circuit model under consideration. In this paper, we describe and compare three of our cone clustering techniques which are based on a formal model of parallel lo gic simulation. Experimental results are given with resp ect to IBM processor structures ranging in their size from several hundred thousand to several million basic elements at a mixture of register-transfer- and gate level.