Performance analysis of multiprocessor architectures in the early design phases is an important task in the development of complex parallel architectures. An approach for the hierarchical modeling and analysis of a wide class of multiprocessor architectures introduced. The technique combines and extends several efficient approaches to analyze large CTMCs underlying hierarchical models of multiprocessor systems. First, the generator matrix is represented in a very compact format which can be exploited in efficient numerical solution techniques. Second, symmetries inherent in most multiprocessor systems can be exploited by generating a CTMC with a smaller state space, which results from exact aggregation. Symmetry exploitation is fully automated and keeps the compact representation of the generator matrix.