Architectural Design Features of a Programmable High Throughput AES Coprocessor

	This Article
	Subscribers, please Login Purchase article: $19 PDF IEEE Xplore Subscribers RSS feed
	Share
	Email this Article to a friend
	Bibliographic References
	ASCII Text BibTex RefWorks Procite/RefMan/Endnote
	Add to:
	Digg Furl Spurl Blink Simpy Google Del.icio.us Y!MyWeb
	Search
	Similar Articles Articles by Alireza Hodjat Articles by Patrick Schaumont Articles by Ingrid Verbauwhede

International Conference on Information Technology: Coding and Computing (ITCC'04) Volume 2

Las Vegas, Nevada

April 05-April 07

ISBN: 0-7695-2108-8

	ASCII Text	x
	Alireza Hodjat, Patrick Schaumont, Ingrid Verbauwhede, "Architectural Design Features of a Programmable High Throughput AES Coprocessor," Information Technology: Coding and Computing, International Conference on, vol. 2, pp. 498, International Conference on Information Technology: Coding and Computing (ITCC'04) Volume 2, 2004.

	BibTex	x
	@article{ 10.1109/ITCC.2004.1286703, author = {Alireza Hodjat and Patrick Schaumont and Ingrid Verbauwhede}, title = {Architectural Design Features of a Programmable High Throughput AES Coprocessor}, journal ={Information Technology: Coding and Computing, International Conference on}, volume = {2}, year = {2004}, isbn = {0-7695-2108-8}, pages = {498}, doi = {http://doi.ieeecomputersociety.org/10.1109/ITCC.2004.1286703}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Information Technology: Coding and Computing, International Conference on TI - Architectural Design Features of a Programmable High Throughput AES Coprocessor SN - 0-7695-2108-8 SP EP A1 - Alireza Hodjat, A1 - Patrick Schaumont, A1 - Ingrid Verbauwhede, PY - 2004 KW - null VL - 2 JA - Information Technology: Coding and Computing, International Conference on ER -

Alireza Hodjat, University of California, Los Angeles

Patrick Schaumont, University of California, Los Angeles

Ingrid Verbauwhede, University of California, Los Angeles

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ITCC.2004.1286703

Programmable, high throughput domain specific crypto processors are required for different networking applications. This paper presents the architectural design features that lead to a multiple Gbits/s rate AES coprocessor, which is programmable with domain specific instructions for Gbit throughput IPSec and other applications. Our design is a loosely coupled, independently working crypto-coprocessor that runs AES in ECB, CBC-MAC, Counter, and CCM modes of operation at a maximum throughput of 3.43 Gbits/s in a 0.18-μm CMOS technology without any penalty in throughput for any of the above modes.

Citation:

Alireza Hodjat, Patrick Schaumont, Ingrid Verbauwhede, "Architectural Design Features of a Programmable High Throughput AES Coprocessor," itcc, vol. 2, pp.498, International Conference on Information Technology: Coding and Computing (ITCC'04) Volume 2, 2004

Peer Review Notice | Give Us Feedback

Usage of this product signifies your acceptance of the Terms of Use.