International Conference on Information Technology: Coding and Computing (ITCC'04) Volume 1 The Effective Buffer Architecture for Data Link Layer of PCI Express Las Vegas, Nevada April 05-April 07 ISBN: 0-7695-2108-8
In this paper, we propose an efficient buffer management scheme to increase performance of the PCI Express architecture. It is necessary for the several buffers such as replay buffer in virtual channel and traffic class buffers to implement the PCI Express architecture. The proposed scheme merges the buffers into only one buffer and dynamically adjusts size of the replay buffer space and traffic class buffers space to effectively support the ordering requirements of the PCI Express. The simulation result shows 30% performance improvement over the conventional scheme that uses separated buffers.
Index Terms:
PCI, PCI Express, Data Link Layer, Buffer, Buffer management
Citation:
Eugin Hyun, Kwang-Su Seong, "The Effective Buffer Architecture for Data Link Layer of PCI Express," itcc, vol. 1, pp.809, International Conference on Information Technology: Coding and Computing (ITCC'04) Volume 1, 2004 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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