International Conference on Information Technology: Coding and Computing (ITCC'04) Volume 1 Semi-Parallel Reconfigurable Architectures for Real-Time LDPC Decoding Las Vegas, Nevada April 05-April 07 ISBN: 0-7695-2108-8
This paper presents a semi-parallel architecture for decoding Low Density Parity Check (LDPC) codes. A modified version of Min-Sum algorithm has been used which has the advantage of simpler computations compared to Sum-Product algorithm without any loss in performance. Special structure of the parity check matrix of the proposed code leads to an efficient semi-parallel implementation of the decoder for a family of (3, 6) LDPC codes. A prototype architecture has been implemented in VHDL on programmable hardware. The design is easily scalable and reconfigurable for larger block sizes. Simulation results show that our proposed decoder for a block length of 1536 bits can achieve data rates up to 127 Mbps.
Index Terms:
Reconfigurable architecture, FPGA imple-mentation, channel coding, parallel architecture, area-time tradeoffs
Citation:
Marjan Karkooti, Joseph R. Cavallaro, "Semi-Parallel Reconfigurable Architectures for Real-Time LDPC Decoding," itcc, vol. 1, pp.579, International Conference on Information Technology: Coding and Computing (ITCC'04) Volume 1, 2004 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb