Direct implementation of serial watershed algorithm based on ordered queue is very slow and consumes a lot of resources. Faster implementation of the algorithm on a chip is difficult owing to a large amount of memory required. In this paper, we propose a modified algorithm which re- quires fifty times less memory compared to the original watershed algorithm by ordered queue, and is also suitable or hardware implementation. Simulation results have been urnished to validate the proposed algorithm. An architecture suitable or FPGA/ASIC implementation is also proposed.