Implementation of a video ranscoder for error resilient video is described. The video protection is based on two methods using frequency domain partitioning and modified H.263++ data partitioning. Moreover, the transcoder uses multiple data packets to communicate a single video frame to the video decoder. The software- based transcoder is implemented on ARM922T RISC processor embedded in Altera Excalibur EPXA10 chip. Neither of video protection methods requires pixel domain decoding/re-encoding, which substantially reduces complexity of the transcoder. Suitability to embedded systems is demonstrated by evaluating memory consumption and benchmarking the application. The effect of overhead of video protection on rate-distortion performance is analysed. The results show that when modified data partitioning is utilised, a 125 MHz ARM922T is able to process 178 frames/s, if hardware/software co-optimisation and QCIF format are used.