The issues of video coding based on exceptionally suitable for SHD format Shapiro EZW (Embedded Zero Wavelet) algorithm is discussed in this paper. The main aspect is a possibility of building a real time system, which is able to process the algorithm. Thus, a dedicated architecture for the purpose is concerned. The method presented below is based on EZW method modified such a way to simplify hardware architecture dedicated for its executing. Such a simplification allows using FPGA technology as a target platform for the system.The MISD (Multiple Instruction-stream Single Data-stream) architecture is proposed as a solution of the problem. The architecture is characterized by high-speed execution of the EZW algorithm. Simplicity and performance classify the algorithm for implementation in high capacity programmable FPGA structures. The presented paper is an author's contribution in world's development of custom computing machines - CCM.