We discuss the development of Built-In Self-Test (BIST) configurations that test all of the programmable logic and interconnect resources in the core of Xilinx 4000E, 4000XL/XLA and Spartan series Field Programmable Gate Arrays (FPGAs). While there has been prior work in BIST for these FPGAs, the fast-carry logic has not been addressed and only a small portion of the total interconnect resources has been targeted. The programmable logic is completely tested in two test sessions of 12 BIST configurations each, but the programmable interconnect resources requires as many as 206 BIST configurations. Therefore, we also discuss architectural features that affect the testability of the FPGA and, in turn, the number of BIST configurations needed by comparing the BIST configurations developed for these Xilinx FPGAs with those previously developed for other FPGAs.