FPGA Interconnect Delay Fault Testing

I
ITC
2003
International Test Conference 2003 (ITC'03)
Abstract - FPGA Interconnect Delay Fault Testing

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International Test Conference 2003 (ITC'03)

Charlotte, NC, USA

September 30-October 02

ISBN: 0-7803-8107-6

	ASCII Text	x
	Erik Chmelar, "FPGA Interconnect Delay Fault Testing," Test Conference, International, pp. 1239, International Test Conference 2003 (ITC'03), 2003.

	BibTex	x
	@article{ 10.1109/TEST.2003.1271113, author = {Erik Chmelar}, title = {FPGA Interconnect Delay Fault Testing}, journal ={Test Conference, International}, volume = {0}, year = {2003}, issn = {1089-3539}, pages = {1239}, doi = {http://doi.ieeecomputersociety.org/10.1109/TEST.2003.1271113}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Test Conference, International TI - FPGA Interconnect Delay Fault Testing SN - 1089-3539 SP EP A1 - Erik Chmelar, PY - 2003 KW - null VL - 0 JA - Test Conference, International ER -

Erik Chmelar, Stanford University

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/TEST.2003.1271113

Interconnection networks consume the majority of die area in an FPGA. Presented is a scalable manufacturing test method for all SRAM-based FPGAs, able to detect multiple interconnect delay faults, multiple bridging faults, or both. An adjustable maximum sensitivity to resistive open defects of several kilo-ohms is achieved. Bridging faults that cause a signal transition to occur one at least one of the bridged interconnects are detectable. Finally, fast and simple fault localization is presented.

Citation:

Erik Chmelar, "FPGA Interconnect Delay Fault Testing," itc, pp.1239, International Test Conference 2003 (ITC'03), 2003

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