This paper presents an approach for reducing the test data volume that has to be stored in ATE vector memory for IC manufacturing testing. We exploit the capabilities of present ATE to assign groups of input pins to ports and to perform vector repeat per port. This allows run-length encoding of test stimuli per port. We improve the encoding by filling the don't-care bits in the test stimuli, such that longer run-lengths are obtained. We provide a probabilistic analysis of the performance of vector repeat per port with various ATPG padding types. We further discuss the impact of ATE architectures. The paper provides experimental data for a set of large industrial circuits, which shows an average reduction of the test stimulus data volume by a factor of 13.