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International Test Conference 2003 (ITC'03)
Overview of the IEEE P1500 Standard
Charlotte, NC, USA
September 30-October 02
ISBN: 0-7803-8107-6
Francisco DaSilva, Synopsys, Inc., Mountain View, CA
Yervant Zorian, Virage Logic, Fremont, CA
Lee Whetsel, Texas Instruments, Dallas, TX
Karim Arabi, PMC Sierra, Burnaby, BC
Rohit Kapur, Synopsys, Inc., Mountain View, CA
Design reuse has been a key enabler to efficient System-On-Chip creation, by allowing pre-designed functions to be leveraged, thereby reducing development cycles and time to market. The test of these pre-designed blocks, often referred to as cores, is a primordial factor to successful design reuse methodologies, and must be considered by anticipation with various degrees of challenges depending on the mergeable or non-mergeable nature of the core. This paper presents the state and accomplishments of the IEEE 1500 proposal for the test of non-mergeable cores.
Citation:
Francisco DaSilva, Yervant Zorian, Lee Whetsel, Karim Arabi, Rohit Kapur, "Overview of the IEEE P1500 Standard," itc, pp.988, International Test Conference 2003 (ITC'03), 2003
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