Power-aware NoC Reuse on the Testing of Core-based Systems

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	Similar Articles Articles by ?rika Cota Articles by Luigi Carro Articles by Fl?vio Wagner Articles by Marcelo Lubaszewski

International Test Conference 2003 (ITC'03)

Charlotte, NC, USA

September 30-October 02

ISBN: 0-7803-8107-6

	ASCII Text	x
	?rika Cota, Luigi Carro, Fl?vio Wagner, Marcelo Lubaszewski, "Power-aware NoC Reuse on the Testing of Core-based Systems," Test Conference, International, pp. 612, International Test Conference 2003 (ITC'03), 2003.

	BibTex	x
	@article{ 10.1109/TEST.2003.1270888, author = {?rika Cota and Luigi Carro and Fl?vio Wagner and Marcelo Lubaszewski}, title = {Power-aware NoC Reuse on the Testing of Core-based Systems}, journal ={Test Conference, International}, volume = {0}, year = {2003}, issn = {1089-3539}, pages = {612}, doi = {http://doi.ieeecomputersociety.org/10.1109/TEST.2003.1270888}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Test Conference, International TI - Power-aware NoC Reuse on the Testing of Core-based Systems SN - 1089-3539 SP EP A1 - ?rika Cota, A1 - Luigi Carro, A1 - Fl?vio Wagner, A1 - Marcelo Lubaszewski, PY - 2003 KW - null VL - 0 JA - Test Conference, International ER -

?rika Cota, Universidade Federal do Rio Grande do Sul

Luigi Carro, Universidade Federal do Rio Grande do Sul

Fl?vio Wagner, Universidade Federal do Rio Grande do Sul

Marcelo Lubaszewski, Universidade Federal do Rio Grande do Sul

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/TEST.2003.1270888

This work discusses the impact of power consumption on the test time of core-based systems, when an available on-chip network is reused as test access mechanism. A previously proposed technique for the reuse of an on-chip network is extended to consider power consumption during test, while minimizing the system testing time. Experimental results with the ITC'02 SoC benchmarks show that although power constraints can preclude the full exploration of the network parallelism, this platform is still a powerful mechanism for the system test time reduction at a very low cost.

Citation:

?rika Cota, Luigi Carro, Fl?vio Wagner, Marcelo Lubaszewski, "Power-aware NoC Reuse on the Testing of Core-based Systems," itc, pp.612, International Test Conference 2003 (ITC'03), 2003

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