Efficient Scan Chain Design for Power Minimization During Scan Testing Under Routing Constraint

I
ITC
2003
International Test Conference 2003 (ITC'03)
Abstract - Efficient Scan Chain Design for Power Minimization During Scan Testing Under Routing Constraint

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	Similar Articles Articles by Y. Bonhomme Articles by P. Girard Articles by L. Guiller Articles by C. Landrault Articles by S. Pravossoudovitch

International Test Conference 2003 (ITC'03)

Charlotte, NC, USA

September 30-October 02

ISBN: 0-7803-8107-6

	ASCII Text	x
	Y. Bonhomme, P. Girard, L. Guiller, C. Landrault, S. Pravossoudovitch, "Efficient Scan Chain Design for Power Minimization During Scan Testing Under Routing Constraint," Test Conference, International, pp. 488, International Test Conference 2003 (ITC'03), 2003.

	BibTex	x
	@article{ 10.1109/TEST.2003.1270874, author = {Y. Bonhomme and P. Girard and L. Guiller and C. Landrault and S. Pravossoudovitch}, title = {Efficient Scan Chain Design for Power Minimization During Scan Testing Under Routing Constraint}, journal ={Test Conference, International}, volume = {0}, year = {2003}, issn = {1089-3539}, pages = {488}, doi = {http://doi.ieeecomputersociety.org/10.1109/TEST.2003.1270874}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Test Conference, International TI - Efficient Scan Chain Design for Power Minimization During Scan Testing Under Routing Constraint SN - 1089-3539 SP EP A1 - Y. Bonhomme, A1 - P. Girard, A1 - L. Guiller, A1 - C. Landrault, A1 - S. Pravossoudovitch, PY - 2003 KW - null VL - 0 JA - Test Conference, International ER -

Y. Bonhomme, LIRMM, Universit? Montpellier II/CNRS, France

P. Girard, LIRMM, Universit? Montpellier II/CNRS, France

L. Guiller, Synopsys Inc., Mountain View, CA

C. Landrault, LIRMM, Universit? Montpellier II/CNRS, France

S. Pravossoudovitch, LIRMM, Universit? Montpellier II/CNRS, France

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/TEST.2003.1270874

Scan-based architectures, though widely used in modern designs, are expensive in power consumption. In this paper, we present a new technique that allows to design power-optimized scan chains under a given routing constraint. The proposed technique is a three-phase process based on clustering and reordering of scan cells in the design. It allows to reduce average power consumption during scan testing. Owing to this technique, short scan connections in scan chains are guaranteed and congestion problems in the design are avoided.

Citation:

Y. Bonhomme, P. Girard, L. Guiller, C. Landrault, S. Pravossoudovitch, "Efficient Scan Chain Design for Power Minimization During Scan Testing Under Routing Constraint," itc, pp.488, International Test Conference 2003 (ITC'03), 2003

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