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International Test Conference 2003 (ITC'03)
Application and Analysis of RT-Level Software-Based Self-Testing for Embedded Processor Cores
Charlotte, NC, USA
September 30-October 02
ISBN: 0-7803-8107-6
N. Kranitis, University of Athens, Greece
G. Xenoulis, University of Piraeus, Greece
A. Paschalis, University of Athens, Greece
D. Gizopoulos, University of Piraeus, Greece
Y. Zorian, Virage Logic, Fremont, CA
Embedded processor testing techniques based on the execution of self-test routines, have been recently proposed as an effective alternative to classical hardware Built-In Self Test. Software-based self-testing provides at-speed testing capability and does not add hardware or performance penalties. It efficiently partitions the testing task between external testers and internal processor resources.
In this paper we analyze the application of a software-based self-testing methodology to different implementations of a complex embedded processor architecture. We demonstrate that such a methodology provides high test quality in different processor implementations with low test development and low test application costs.
Citation:
N. Kranitis, G. Xenoulis, A. Paschalis, D. Gizopoulos, Y. Zorian, "Application and Analysis of RT-Level Software-Based Self-Testing for Embedded Processor Cores," itc, pp.431, International Test Conference 2003 (ITC'03), 2003
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