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International Test Conference 2003 (ITC'03)
Optical and Electrical Testing of Latchup in I/O Interface Circuits
Charlotte, NC, USA
September 30-October 02
ISBN: 0-7803-8107-6
Franco Stellari, IBM T.J. Watson Research Center, Yorktown Heights, NY
Peilin Song, IBM T.J. Watson Research Center, Yorktown Heights, NY
Moyra K. McManus, IBM T.J. Watson Research Center, Yorktown Heights, NY
Robert Gauthier, IBM Microelectronics Semiconductor and Research Development Center, Essex Junction, VT
Alan J. Weger, IBM T.J. Watson Research Center, Yorktown Heights, NY
Kiran Chatty, IBM Microelectronics Semiconductor and Research Development Center, Essex Junction, VT
Mujahid Muhammad, IBM Microelectronics Semiconductor and Research Development Center, Essex Junction, VT
Pia Sanda, IBM Systems Group, Poughkeepsie, NY
Backside light emission and electrical measurements were used to evaluate the susceptibility to latchup of externally cabled I/O pins for a 0.13 ?m technology generation [1,2] test chip, which was designed in a flip-chip package. Case studies of several Inputs/Outputs (I/Os) are shown along with conclusions regarding layout and floorplanning to ensure the robustness to various types of latchup trigger events.
Citation:
Franco Stellari, Peilin Song, Moyra K. McManus, Robert Gauthier, Alan J. Weger, Kiran Chatty, Mujahid Muhammad, Pia Sanda, "Optical and Electrical Testing of Latchup in I/O Interface Circuits," itc, pp.236, International Test Conference 2003 (ITC'03), 2003
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