As the sampling frequency of new ADCs and DACs increases, it gets more difficult to accurately convey the analog stimulus or response to or from the converter under test - there is a bandwidth bottleneck. This paper describes a technique that uses a < 100 kHz analog bus, such as the standard 1149.4 bus, to convey an arbitrary analog signal, and converts the signal to or from a high frequency at the converter, on-chip. This permits existing low-frequency distortion tests, both ATE-based and embedded, to be used for high frequency converters. High frequency noise is easily filtered out, permitting a more repeatable test and the use of low cost testers. A hypothetical 100 MHz, 14-bit ADC and DAC are used as examples. The technique has reduced sensitivity to sampling jitter, and 16~18 bit linearity appears feasible.