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International Test Conference 2003 (ITC'03)
Fault Injection for Verifying Testability at the VHDL Level
Charlotte, NC, USA
September 30-October 02
ISBN: 0-7803-8107-6
S. R. Seward, University of Arkansas, Fayetteville
P. K. Lala, University of Arkansas, Fayetteville
This paper presents a technique to improve verification at the VHDL level of digital circuits by means of a specially designed fault injection block. The injection technique allows incorporation of both transient and permanent faults to varying levels of VHDL hierarchy, and helps in verifying the performance of a testable system.
Citation:
S. R. Seward, P. K. Lala, "Fault Injection for Verifying Testability at the VHDL Level," itc, pp.131, International Test Conference 2003 (ITC'03), 2003
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