A technique to derive test vectors that exercise the worst-case delay effects in a domino circuit in the presence of crosstalk is described. A model for characterizing the delay of a domino gate in the presence of crosstalk is developed and exploited by a new efficient timing analysis algorithm. The algorithm uses a single, breadth-first traversal to compute delays in the presence of crosstalk. Thus, it avoids the iterative methods commonly employed for static CMOS circuits. The timing analysis technique is used to generate test input vectors that exercise the worst-case delays of a multi-plier circuit implemented using domino logic. Hspice simulation results demonstrate that the technique identifies test vectors that produce circuit delay that satisfy the targeted value in the presence of crosstalk.