International Test Conference 2003 (ITC'03)
Transistor-Level Fault Analysis and Test Algorithm Development for Ternary Dynamic Content Addressable Memories
Charlotte, NC, USA
September 30-October 02
ISBN: 0-7803-8107-6
Content addressable memories (CAMs) are gaining popularity with computer networks. Testing costs of CAMs are extremely high owing to their unique configuration. In this paper, we carried out a transistor-level fault analysis and devise a search path test algorithm. The proposed algorithm is of the order (nl / log2n) compared to the brute-force algorithm of complexity (nl). For the analyzed CAM, the search path test complexity is reduced by 30x.
Citation:
Derek Wright, Manoj Sachdev, "Transistor-Level Fault Analysis and Test Algorithm Development for Ternary Dynamic Content Addressable Memories," itc, pp.39, International Test Conference 2003 (ITC'03), 2003