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International Test Conference 2002 (ITC'02)
Adapting an SoC to ATE Concurrent Test Capabilities
Baltimore, MD, USA
October 07-October 10
ISBN: 0-7803-7543-2
Rainer Dorsch, University of Stuttgart
Ram?n Huerta Rivera, University of Stuttgart
Hans-Joachim Wunderlich, University of Stuttgart
Martin Fischer, Agilent Technologies
Concurrent test features are available in the SoC testers to increase ATE throughput. To exploit these new features design modifications are necessary. In a case study, these modifications were applied to the open source LEON SoC platform containing an embedded 32 bit CPU, an AMBA bus, and several embedded cores. The concurrent test of LEON was performed on an SoC tester. The gain in test application time and area costs are quantified and obstacles in the design flow or concurrent test are discussed.
Index Terms:
ATE, Concurrent Test, SoC Test, Test Resource Partitioning
Citation:
Rainer Dorsch, Ram?n Huerta Rivera, Hans-Joachim Wunderlich, Martin Fischer, "Adapting an SoC to ATE Concurrent Test Capabilities," itc, pp.1169, International Test Conference 2002 (ITC'02), 2002
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