A DFT Technique for Low Frequency Delay Fault Testing in High Performance Digital Circuits

I
ITC
2002
International Test Conference 2002 (ITC'02)
Abstract - A DFT Technique for Low Frequency Delay Fault Testing in High Performance Digital Circuits

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International Test Conference 2002 (ITC'02)

Baltimore, MD, USA

October 07-October 10

ISBN: 0-7803-7543-2

	ASCII Text	x
	Bhaskar Chatterjee, Manoj Sachdev, Ali Keshavarzi, "A DFT Technique for Low Frequency Delay Fault Testing in High Performance Digital Circuits," Test Conference, International, pp. 1130, International Test Conference 2002 (ITC'02), 2002.

	BibTex	x
	@article{ 10.1109/TEST.2002.1041870, author = {Bhaskar Chatterjee and Manoj Sachdev and Ali Keshavarzi}, title = {A DFT Technique for Low Frequency Delay Fault Testing in High Performance Digital Circuits}, journal ={Test Conference, International}, volume = {0}, year = {2002}, isbn = {0-7803-7543-2}, pages = {1130}, doi = {http://doi.ieeecomputersociety.org/10.1109/TEST.2002.1041870}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Test Conference, International TI - A DFT Technique for Low Frequency Delay Fault Testing in High Performance Digital Circuits SN - 0-7803-7543-2 SP EP A1 - Bhaskar Chatterjee, A1 - Manoj Sachdev, A1 - Ali Keshavarzi, PY - 2002 KW - null VL - 0 JA - Test Conference, International ER -

Bhaskar Chatterjee, University of Waterloo

Manoj Sachdev, University of Waterloo

Ali Keshavarzi, Intel Labs

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/TEST.2002.1041870

This paper presents a DFT technique for delay fault testing of high performance, dynamic CMOS circuits. A high performance, delay fault testable, 16-bit adder is designed in 0.18 ?m CMOS technology. Simulations for the adder demonstrate that this technique can detect delay faults greater than 35ps and improves delay fault detection capability. It also allows at least 10X reduction in test mode clock frequency. Furthermore, the proposed method is capable of providing delay fault diagnostics. However, the proposed DFT technique increases delay by 8.6% with minimal power penalty.

Citation:

Bhaskar Chatterjee, Manoj Sachdev, Ali Keshavarzi, "A DFT Technique for Low Frequency Delay Fault Testing in High Performance Digital Circuits," itc, pp.1130, International Test Conference 2002 (ITC'02), 2002

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