A New Test Generation Approach for Embedded Analogue Cores in SoC

I
ITC
2002
International Test Conference 2002 (ITC'02)
Abstract - A New Test Generation Approach for Embedded Analogue Cores in SoC

	This Article
	Subscribers, please Login Purchase article: $19 PDF IEEE Xplore Subscribers RSS feed
	Share
	Email this Article to a friend
	Bibliographic References
	ASCII Text BibTex RefWorks Procite/RefMan
	Add to:
	Digg Furl Spurl Blink Simpy Google Del.icio.us Y!MyWeb
	Search
	Similar Articles Articles by M. Stancic Articles by L. Fang Articles by M. H. H. Weusthof Articles by R. M. W. Tijink Articles by H. G. Kerkhoff

International Test Conference 2002 (ITC'02)

Baltimore, MD, USA

October 07-October 10

ISBN: 0-7803-7543-2

	ASCII Text	x
	M. Stancic, L. Fang, M. H. H. Weusthof, R. M. W. Tijink, H. G. Kerkhoff, "A New Test Generation Approach for Embedded Analogue Cores in SoC," Test Conference, International, pp. 861, International Test Conference 2002 (ITC'02), 2002.

	BibTex	x
	@article{ 10.1109/TEST.2002.1041840, author = {M. Stancic and L. Fang and M. H. H. Weusthof and R. M. W. Tijink and H. G. Kerkhoff}, title = {A New Test Generation Approach for Embedded Analogue Cores in SoC}, journal ={Test Conference, International}, volume = {0}, year = {2002}, isbn = {0-7803-7543-2}, pages = {861}, doi = {http://doi.ieeecomputersociety.org/10.1109/TEST.2002.1041840}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Test Conference, International TI - A New Test Generation Approach for Embedded Analogue Cores in SoC SN - 0-7803-7543-2 SP EP A1 - M. Stancic, A1 - L. Fang, A1 - M. H. H. Weusthof, A1 - R. M. W. Tijink, A1 - H. G. Kerkhoff, PY - 2002 KW - null VL - 0 JA - Test Conference, International ER -

M. Stancic, University of Twente

L. Fang, University of Twente

M. H. H. Weusthof, University of Twente

R. M. W. Tijink, University of Twente

H. G. Kerkhoff, University of Twente

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/TEST.2002.1041840

This paper proposes a new test-generation approach for embedded analogue cores in SoC. The key features of this approach are the developed testability-analysis based multi-frequency test pattern generation method, the novel PID feedback-based test signal backtrace procedure and the fast tolerance-box propagation algorithm. Moreover, possible DfT solutions are discussed. Finally, this approach has been validated by experiments conducted on a real hardware implementation.

Citation:

M. Stancic, L. Fang, M. H. H. Weusthof, R. M. W. Tijink, H. G. Kerkhoff, "A New Test Generation Approach for Embedded Analogue Cores in SoC," itc, pp.861, International Test Conference 2002 (ITC'02), 2002

Peer Review Notice | Give Us Feedback

Usage of this product signifies your acceptance of the Terms of Use.