Significant reductions in test application times can be achieved through parallelizing core tests; however, simultaneous test of various cores may result in exceeding power thresholds, endangering the SOC being tested. Test power dissipation is exceedingly high in scan-based environments wherein scan chain transitions during the shift of test data further reflect into significant levels of circuit switching unnecessarily. Scan chain modification helps mitigate this problem as it enables the reduction of transitions in the test stimuli to be inserted to the modified scan chain and in the response to be collected through the scan-out pin. The proposed modifications in the scan chain consist of inverter insertion and scan cell reordering, leading to significant power reductions with neither area nor performance penalty whatsoever. A computationally efficient algorithm is presented to identify the optimal scan chain modification based on the transition frequency analysis of the test data. Experimental results confirm the considerable reductions in scan chain transitions. The consequent reduced power dissipation possible under the proposed scheme enables rapid, reliable testing of SOCs.