The industry's adoption of powerful design methodologies, such as physical synthesis, formal verification, and static timing analysis are speeding the implementation and verification of multi-million gate ASICs and System-on-Chip (SoC). As the design community moves to the complete adoption of a physical synthesis flow, it is becoming evident that test synthesis must be cognizant of layout issues and well integrated within physical design tools. By bringing in key physical functions into the front-end of the DFT/physical synthesis flow, the designer is able to successfully meet all design and testability goals, with minimum impact on timing closure.

In this paper, we present a DFT synthesis flow tightly integrated within Physical synthesis to achieve physically optimized scan designs. This flow describes new test technology which uses physical information to achieve optimal scan chain partitioning, timing-driven scan ordering and DFT driven placement to dramatically reduce routing congestion, and achieve a rapid and predictable timing closure.