This paper validates an integrated yield-reliability model for redundant memory using yield and stress test data from a 36 Mbit SRAM memory chip and an 8 Mbit embedded DRAM chip. These products were manufactured by IBM Microelectronics in Burlington, Vermont. In both cases, those chips determined functional following wafer test and repair were subjected to voltage stress and burn-in. It will be shown that the yield-reliability model can accurately model not only the fraction of die with 0, 1, 2, ... repairs, but also predict the number of stress test failures for a die with a given number of repairs. Because defects in integrated circuits tend to cluster, it has been suspected that repaired die have a greater chance of containing early-life reliability defects than die with no repairs. Repaired die should therefore be more likely to fail stress tests than die with no repairs. This work presents the first experimental validation of these statements. In particular, experimental results indicate that, as predicted by the yield-reliability model, the stress test failure probability is linearly related to the number of repairs; the slope of this line is intimately related to the degree to which defects cluster over the wafer. Model predictions are in excellent agreement with observed data.