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International Test Conference 2002 (ITC'02)
Wafer-Level Defect-Based Testing Using Enhanced Voltage Stress and Statistical Test Data Evaluation
Baltimore, MD, USA
October 07-October 10
ISBN: 0-7803-7543-2
Minh Quach, Agilent Technologies Company
Tuan Pham, Agilent Technologies Company
Tim Figal, Agilent Technologies Company
Bob Kopitzke, Agilent Technologies Company
Pete O?Neill, Agilent Technologies Company
In this paper, we illustrate the effectiveness of wafer-level Enhanced Voltage Stress (EVS) along with Low Voltage Sweep (LVS), IDDQ and other parametric tests to screen early life failure defects. Our experiment shows temporary undetected defects after repeated exposure to certain applied voltages. We demonstrate a statistical methodology to screen die with suspected early life failure defects.
Citation:
Minh Quach, Tuan Pham, Tim Figal, Bob Kopitzke, Pete O?Neill, "Wafer-Level Defect-Based Testing Using Enhanced Voltage Stress and Statistical Test Data Evaluation," itc, pp.683, International Test Conference 2002 (ITC'02), 2002
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