This paper presents the DFT techniques used in Motorola?s high performance e500 core, which implements the PowerPC "Book E" architecture and is designed to run at 600 MHz to 1 GHz. Highlights of the DFT features are at-speed logic built-in self-test (LBIST) for delay fault detection, very high test coverage for scan based at-speed deterministic delay-fault test patterns, 100% BIST for embedded memory arrays and 99.2% stuck-at fault test coverage for deterministic scan test patterns. A salient design feature is the isolation ring that facilitates testing of the core when it is integrated in an SoC or host processor.