International Test Conference 2002 (ITC'02) Complete, Contactless I/O Testing — Reaching the Boundary in Minimizing Digital IC Testing Cost Baltimore, MD, USA October 07-October 10 ISBN: 0-7803-7543-2
Embedded test of memory and random logic can enable very low cost ATE to test large, high speed ICs because high quality at-speed tests can be generated on-chip. However, it is also necessary to test the DC and AC parameters of the input/output (I/O) circuitry. This paper describes how most I/O pin characteristics can be tested cost-effectively with a variety of novel techniques that exploit the 1149.1 and 1149.4 test standards. The techniques measure VOL/IOL, VOH/IOH, VIH, and VIL at DC, perform at-speed I/O wrap, and test on-chip power rail impedance, all via minimum pin-count (MPC) access. The 1149.4 bus is also suitable, of course, for testing mixed-signal functions. The paper then discusses costs and benefits of MPC testing of high pin-count ICs on low cost tester to show that testing costs can be reduced to insignificance.
Citation:
Stephen K. Sunter, Benoit Nadeau-Dostie, "Complete, Contactless I/O Testing — Reaching the Boundary in Minimizing Digital IC Testing Cost," itc, pp.446, International Test Conference 2002 (ITC'02), 2002 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||