Design-For-Test (DFT) techniques for acquiring fail bit map of at-speed function with conventional wafer test equipment are proposed. SRAM core is operated with high-frequency clock generated by gain-suppressed VCO which can reduce clock jitter. The data are output with data out strobe control circuit synchronizing with external low-frequency clock. Using these techniques, the SRAM chip appears to be operated with low-frequency tester clock while SRAM core is operated with high-frequency internal clock. Therefore, fail bit map of high-frequency operation can be obtained with conventional wafer test equipment. The at-speed test with fail bit map acquisition allows slow bit cell replacement to spare cell or chip-by-chip internal timing optimization with fuse-blowing. It results in a drastic reduction in test cost and performance yield improvement.