FPGA Placement and Routing Using Particle Swarm Optimization

I
ISVLSI
2004
IEEE Computer Society Annual Symposium on VLSI: Emerging Trends in VLSI Systems Design (ISVLSI'04)
Abstract - FPGA Placement and Routing Using Particle Swarm Optimization

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IEEE Computer Society Annual Symposium on VLSI: Emerging Trends in VLSI Systems Design (ISVLSI'04)

FPGA Placement and Routing Using Particle Swarm Optimization (PDF)

Lafayette, Louisiana

February 19-February 20

ISBN: 0-7695-2097-9

	ASCII Text	x
	Venu G. Gudise, Ganesh K. Venayagamoorthy, "FPGA Placement and Routing Using Particle Swarm Optimization," VLSI, IEEE Computer Society Annual Symposium on, pp. 307, IEEE Computer Society Annual Symposium on VLSI: Emerging Trends in VLSI Systems Design (ISVLSI'04), 2004.

	BibTex	x
	@article{ 10.1109/ISVLSI.2004.1339567, author = {Venu G. Gudise and Ganesh K. Venayagamoorthy}, title = {FPGA Placement and Routing Using Particle Swarm Optimization}, journal ={VLSI, IEEE Computer Society Annual Symposium on}, volume = {0}, year = {2004}, isbn = {0-7695-2097-9}, pages = {307}, doi = {http://doi.ieeecomputersociety.org/10.1109/ISVLSI.2004.1339567}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI, IEEE Computer Society Annual Symposium on TI - FPGA Placement and Routing Using Particle Swarm Optimization SN - 0-7695-2097-9 SP EP A1 - Venu G. Gudise, A1 - Ganesh K. Venayagamoorthy, PY - 2004 KW - null VL - 0 JA - VLSI, IEEE Computer Society Annual Symposium on ER -

Venu G. Gudise, University of Missouri-Rolla

Ganesh K. Venayagamoorthy, University of Missouri-Rolla

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ISVLSI.2004.1339567

Field programmable gate arrays (FPGAs) are becoming increasingly important implementation platforms for digital circuits. One of the necessary requirements to effectively utilize the FPGA?s fixed resources is an efficient placement and routing mechanism. This paper presents particle swarm optimization (PSO) for FPGA placement and routing. Preliminary results for the implementation of an arithmetic logic unit on a Xilinx FPGA show that PSO is a potential technique for solving the placement and routing problem.

Citation:

Venu G. Gudise, Ganesh K. Venayagamoorthy, "FPGA Placement and Routing Using Particle Swarm Optimization," isvlsi, pp.307, IEEE Computer Society Annual Symposium on VLSI: Emerging Trends in VLSI Systems Design (ISVLSI'04), 2004

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