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IEEE Computer Society Annual Symposium on VLSI: Emerging Trends in VLSI Systems Design (ISVLSI'04)
Lafayette, Louisiana
February 19-February 20
ISBN: 0-7695-2097-9
Chandrasekar Rajagopal, Syracuse University
Adrián Núñez-Aldana, Syracuse University
In this paper, we present a methodology to design analog circuits and program the circuits using a digital bit stream to function like a desired complex circuit (ex. OTAs). The basic CMOS analog cells are synthesized from high-level circuit specifications into transistor net-lists using a two phase tuning process. The first phase uses a fast analog performance estimator to perform a global circuit sizing and the second phase involves Spice circuit simulations for a detail circuit sizing achieving high accuracy results. The synthesis environment relies on a genetic algorithm based heuristic method to search for a solution in a large designspace.
Citation:
Chandrasekar Rajagopal, Adrián Núñez-Aldana, "CMOS Analog Programmable Logic Array," isvlsi, pp.291, IEEE Computer Society Annual Symposium on VLSI: Emerging Trends in VLSI Systems Design (ISVLSI'04), 2004
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