A Memory Aware High Level Synthesis Tool

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IEEE Computer Society Annual Symposium on VLSI: Emerging Trends in VLSI Systems Design (ISVLSI'04)

A Memory Aware High Level Synthesis Tool (PDF)

Lafayette, Louisiana

February 19-February 20

ISBN: 0-7695-2097-9

	ASCII Text	x
	Gwenol? Corre, Eric Senn, Nathalie Julien, Eric Martin, "A Memory Aware High Level Synthesis Tool," VLSI, IEEE Computer Society Annual Symposium on, pp. 279, IEEE Computer Society Annual Symposium on VLSI: Emerging Trends in VLSI Systems Design (ISVLSI'04), 2004.

	BibTex	x
	@article{ 10.1109/ISVLSI.2004.1339557, author = {Gwenol? Corre and Eric Senn and Nathalie Julien and Eric Martin}, title = {A Memory Aware High Level Synthesis Tool}, journal ={VLSI, IEEE Computer Society Annual Symposium on}, volume = {0}, year = {2004}, isbn = {0-7695-2097-9}, pages = {279}, doi = {http://doi.ieeecomputersociety.org/10.1109/ISVLSI.2004.1339557}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI, IEEE Computer Society Annual Symposium on TI - A Memory Aware High Level Synthesis Tool SN - 0-7695-2097-9 SP EP A1 - Gwenol? Corre, A1 - Eric Senn, A1 - Nathalie Julien, A1 - Eric Martin, PY - 2004 KW - null VL - 0 JA - VLSI, IEEE Computer Society Annual Symposium on ER -

Gwenol? Corre, University of South-Brittany

Eric Senn, University of South-Brittany

Nathalie Julien, University of South-Brittany

Eric Martin, University of South-Brittany

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ISVLSI.2004.1339557

We introduce a new approach to take into account the memory architecture and the memory mapping in High-Level Synthesis for data intensive applications. We formalize the memory mapping as a set of constraints for the synthesis, and defined a Memory Constraint Graph and an accessibility criterion to be used in the scheduling step. We use a memory mapping file to include those memory constraints in our HLS tool GAUT. It is possible, with the help of GAUT, to explore a wide range of solutions, and to reach a good tradeoff between time, power-consumption, and area.

Citation:

Gwenol? Corre, Eric Senn, Nathalie Julien, Eric Martin, "A Memory Aware High Level Synthesis Tool," isvlsi, pp.279, IEEE Computer Society Annual Symposium on VLSI: Emerging Trends in VLSI Systems Design (ISVLSI'04), 2004

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